The present invention generally relates to printed wiring boards and more specifically to printed wiring boards having localized regions with different coefficients of thermal expansion (CTEs).
Printed wiring boards can be used to establish electrical connections between devices. In some instances, the devices can be mounted on the printed wiring board. The manner in which the devices are mounted is typically dependent upon the packaging of the device. Examples of packages used for electronic devices include Dual Inline Packages, Small Outline Packages, Thin Small Outline Packages (TSOP), Plastic Packages, Leadless Ceramic Chip Carriers, Ceramic Packages, Ball Grid Array Packages (BGA), Pin Grid Arrays (PGA), Pad Array Carriers (PAC), Micro Ball Grid Arrays, Flip Chip Packages (FC), Chip Scale Packages (CSP) and Wafer Level Packaging (WLP).
Different package types can have significantly different CTEs. An important aspect of printed wiring board design is matching the CTE of the board to the CTE of the packaging of the electronic devices mounted on the printed wiring board. This design objective is often referred to as minimizing CTE mismatch between a printed wiring board and an electronic device's packaging. If mismatches occur, then thermal cycling can cause the electronic device to separate from the printed wiring board. U.S. Pat. No. 6,869,664 to Vasoya et al. and U.S. patent application Ser. No. 11/131,130 disclose techniques that can be used to manufacture printed wiring boards having a desired CTE. The disclosure of U.S. Pat. No. 6,869,664 and U.S. patent application Ser. No. 11/131,130 is incorporated herein by reference in its entirety.